IBM bets on bicycle codes for the first large-scale fault-tolerant quantum computer, and sets a date

IBM has committed to a date and a number. By 2029, they say, they will deliver IBM Quantum Starling: a fault-tolerant quantum machine running 100 million gates on 200 logical qubits, built in Poughkeepsie, New York.

That is a striking target. Today's best superconducting machines run circuits of around 5,000 two-qubit gates and have no proper error correction at all, only mitigation. Starling would be roughly four orders of magnitude further on in circuit depth, on a system that actively suppresses logical errors instead of merely averaging over them.

To back the claim, IBM has released two papers: a full architectural blueprint for the machine, and a new error-correction decoder small enough to fit on an FPGA.

The architecture paper opens with a checklist. To count as a usable fault-tolerant quantum computer, a machine must satisfy six criteria. These are not vague aspirations. Each maps to specific hardware or software the system has to ship.

IBM's argument is that the bicycle architecture, built around their 2024 bivariate bicycle codes, is the only design currently on the table that meets all six and scales.

The six criteria from IBM's architecture paper:

1. Fault-tolerantLogical errors are suppressed enough for meaningful algorithms to succeed.
2. AddressableIndividual logical qubits can be prepared or measured throughout the computation.
3. UniversalA universal set of quantum instructions can be applied to the logical qubits.
4. AdaptiveMeasurements are decoded in real time and can alter subsequent quantum instructions.
5. ModularHardware is distributed across replaceable modules connected quantumly.
6. EfficientMeaningful algorithms can be executed with reasonable physical resources.

The protagonist is the gross code: a [[144, 12, 12]] quantum low-density parity check code, where 144 physical data qubits encode 12 logical qubits at distance 12. Add 144 syndrome check qubits and you have spent 288 physical qubits to protect a dozen logical ones.

At the same distance, IBM claims the surface code (the field's previous default) needs roughly ten times the qubits to do the same job. That is a large overhead saving, paid for by demanding longer-range qubit-to-qubit connections than a flat 2D chip naturally allows. IBM's answer is c-couplers within a chip and l-couplers between chips.

On top of the memory sit logical processing units that perform Clifford gates via generalized lattice surgery, and magic state factory modules that supply the non-Clifford T gates. Universal adapters glue the modules together. Strung along, the components form a complete fault-tolerant instruction set.

There is a subtle catch in error correction. You can detect errors all you like, but if your decoder takes seconds to interpret the syndromes, the qubits will have decohered before you have finished thinking.

The companion paper introduces Relay-BP, an improved belief-propagation decoder that achieves a 5× to 10× reduction in size over leading alternatives while remaining accurate. It is small enough to fit on an FPGA or ASIC. That is what makes real-time decoding plausible without recruiting a small HPC cluster behind every quantum chip.

The roadmap is dense, but the through-line is cleanly named after birds. Loon arrives in 2025 with c-couplers to test high-rate qLDPC connectivity. Kookaburra in 2026 is the first chip to pair a qLDPC memory with a logical processing unit. Cockatoo in 2027 demonstrates entanglement between modules using the universal adapter. Starling proper appears in 2028 with proof-of-concept magic state injection, and in 2029 as the full 200 logical qubit machine.

Running alongside is Nighthawk, a 120-qubit square-lattice processor shipping later this year. Where Heron's heavy-hex lattice gives each qubit two or three neighbours, Nighthawk's square lattice gives four, and IBM claims this delivers roughly 16× the effective circuit depth. By 2028, nine Nighthawk modules linked by l-couplers will reach 1,080 connected qubits running 15,000-gate circuits.

IBM expects the Nighthawk side of the roadmap to deliver real quantum advantage by the end of 2026, well before fault tolerance lands. Whether the rest holds depends on the next four chips arriving on schedule.