Quantum memory gets surface-code thresholds, but with a tenth of the qubits

Quantum error correction already has a good theoretical answer: spread one logical qubit across many noisy physical qubits, measure parity checks repeatedly, and decode the error history before it corrupts the logical state. The practical problem is the bill. Surface codes tolerate realistic noise and fit two-dimensional hardware, but they buy that comfort with poor encoding efficiency.

This paper attacks that cost directly. The authors build fault-tolerant memory from quantum low-density parity-check codes, specifically a new family called bivariate bicycle codes. The pitch is deliberately narrow and useful: not a universal computer, not a grand architecture manifesto, but a memory block that can store logical qubits with much lower physical-qubit overhead.

A BB code with parameters [[n, k, d]] encodes k logical qubits into n data qubits with distance d. The implementation also uses n ancillary check qubits, so the physical total is 2n. The strongest near-term example in the main text, [[144, 12, 12]], stores 12 logical qubits using 288 physical qubits in total.

The catch is connectivity. These checks are not geometrically local like surface-code plaquettes. Each check touches six qubits, and each physical qubit participates in six checks. The paper's key hardware move is showing that the Tanner graph has thickness two: it can be decomposed into two edge-disjoint planar degree-3 layers. That does not make the wiring easy, but it makes it a specific engineering problem rather than a vague impossibility.

The proposed memory stack has four moving parts:

• Bivariate bicycle codeA CSS LDPC code with weight-6 checks and high encoding efficiency at small block sizes.
• Depth-7 syndrome circuitA repeated measurement cycle using seven CNOT layers, plus initialization and measurement.
• BP-OSD decoderBelief propagation with ordered statistics decoding, adapted here to the full circuit noise model.
• Load-store accessLogical measurements connect the BB memory to a surface-code qubit using a Tanner-graph extension.

Under the standard circuit-based noise model, the reported BB examples reach pseudo-thresholds from 0.48% to 0.69%. The largest table entry, [[288, 12, 18]], has pL = 2 x 10^-12 at physical error p = 10^-3, and 10^-22 at p = 10^-4. Those are simulation results, not lab data, but they are the sort of numbers that make hardware teams pay attention.

The more striking comparison is the 12-logical-qubit memory. At p = 10^-3, the [[144, 12, 12]] BB code gives pL = 2 x 10^-7, enough to preserve 12 logical qubits for nearly one million syndrome cycles. The paper states that a surface-code construction would need nearly 3,000 physical qubits to reach the same target. The BB version needs 288. That is the whole argument in one unpleasantly small ratio.

The paper is candid about what has to change. A BB memory needs a low-loss second coupling layer, qubits with seven connections including control, and long-range couplers. For superconducting hardware, the authors argue that tuneable couplers and two-sided packaging make this plausible, while long-range buses remain the hardest part.

That caveat matters. This is not a claim that LDPC memory can be dropped into today's chips unchanged. It is a claim that the most painful surface-code tax may not be fundamental, and that a near-term demonstration of low-overhead fault-tolerant memory can be aimed at hundreds of physical qubits rather than several thousand. Modest, by quantum computing standards, which is to say still fairly heroic.